spread aware?, ten/eleven output zero delay buffe r cy2509/10 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07230 rev. *c revised july 01, 2005 features ? spread aware??designed to work with ssftg reference signals ? well suited to both 100- and 133-mhz designs ? ten (cy2509) or eleven (cy2510) lvcmos/lvttl outputs ? 50 ps typical peak cycle-to-cycle jitter ? single output enable pin for cy2510 version, dual pins on cy2509 devices allow shutting down a portion of the outputs ? 3.3v power supply ? on board 25 ? damping resistors ? available in 24-pin tssop package ? improved tracking skew, but narrower frequency support limit when compared to w132-09b/10b key specifications operating voltage: ................................................3.3v10% operating range: ....................... 40 mhz < f out < 140 mhz cycle-to-cycle jitter: ................................................ <100 ps output to output skew: ........................................... <100 ps phase error jitter:..................................................... <100 ps block diagram pin configurations q0 pll q1 q2 q3 q5 q6 oe0:4 q7 q8 fbout q4 q9 oe oe5:8 configuration of these blocks dependent upon specific option being used fbin clk clk avdd vdd q9 q8 gnd gnd q7 q6 q5 vdd fbin 24 23 22 21 20 19 18 17 16 15 14 13 agnd vdd q0 q1 q2 gnd gnd q3 q4 vdd oe fbout 1 2 3 4 5 6 7 8 9 10 11 12 cy2510 clk avdd vdd q8 q7 gnd gnd q6 q5 vdd oe5:8 fbin 24 23 22 21 20 19 18 17 16 15 14 13 agnd vdd q0 q1 q2 gnd gnd q3 q4 vdd oe0:4 fbout 1 2 3 4 5 6 7 8 9 10 11 12 cy2509 [+] feedback
cy2509/10 document #: 38-07230 rev. *c page 2 of 6 overview the cy2509/10 is a pll-based clock driver designed for use in dual inline memory modules. the clock driver has output frequencies of up to 133 mhz a nd output to output skews of less than 250 ps. the cy2509/10 provides minimum cycle-to- cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in dimm applica- tions. the current generation of 256- and 512-megabyte memory modules needs to support 100-mhz clocking speeds. especially for cards configured in 16x4 or 8x8 format, the clock signal provided from the moth erboard is generally not strong enough to meet all the requirements of the memory and logic on the dimm. the cy2509/10 takes in the signal from the motherboard and buffers out clock signals with enough drive to support all the dimm board clocking needs. the cy2509/10 is also designed to meet the needs of new pc133 sdram designs, operating to 133 mhz. the cy2509/10 was specifically designed to accept ssftg signals currently being used in motherboard designs to reduce emi. zero delay buffers which are not designed to pass this feature through may cause skewing failures. output enable pins allow for shutdown of output when they are not being used. this reduces emi and power consumption. pin definitions pin name pin no. (2509) pin no. (2510) pin type pin description clk 24 24 i reference input: output signals q0:9 will be synchronized to this signal. fbin 13 13 i feedback input: this input must be fed by one of the outputs (typically fbout) to ensure proper functionality. if the tr ace between fbin and fbout is equal in length to the traces between the output s and the signal dest inations, then the signals received at the destinations will be synchronized to the clk signal input. q0:8 3, 4, 5, 8, 9, 16, 17, 20, 21 3, 4, 5, 8, 9, 15, 16, 17, 20 o integrated series resistor outputs: the frequency and phase of the signals provided by these pins will be equal to the reference signal if properly laid out. each output has a 25 ? series damping resistor integrated. q9 n/a 21 o integrated series resistor output: the frequency and phase of the signal provided by this pin will be equal to the re ference signal if properly laid out. this output has a 25 ? series damping resistor integrated. fbout 12 12 o feedback output: this output has a 25 ? series resistor integrated on chip. typically it is connected directly to the fbin input with a trace equal in length to the traces between outputs q0:9 and the destination point s of these output signals. avdd 23 23 p analog power connection: connect to 3.3v. use ferrite beads to help reduce noise for optimal jitter performance. agnd 1 1 g analog ground connection: connect to common system ground plane. vdd 2, 10, 15, 22 2, 10, 14, 22 p power connections: connect to 3.3v. use ferrite beads to help reduce noise for optimal jitter performance. gnd 6, 7, 18, 19 6, 7, 18, 19 g ground connections: connect to common system ground plane. oe n/a 11 i output enable input: tie to vdd (high, 1) for normal operation. when brought to gnd (low, 0) all outputs are disabled to a low state. oe0:4 11 n/a i output enable input: tie to vdd (high, 1) for normal operation. when brought to gnd (low, 0) outputs q0:4 are disabled to a low state. oe5:8 14 n/a i output enable input: tie to vdd (high, 1) for normal operation. when brought to gnd (low, 0) outputs q5:8 are disabled to a low state. [+] feedback
cy2509/10 document #: 38-07230 rev. *c page 3 of 6 spread aware? many systems being designed now utilize a technology called spread spectrum frequency ti ming generation. cypress has been one of the pioneers of ssftg development, and we designed this product so as not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the ss feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. for more details on spread spectrum timing technology, please see the cypress application note titled, ?emi suppression techniques with spread spectrum frequency timing generator (ssftg) ics.? how to implement zero delay typically, zero delay buffers (zdbs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. the whole concept behind zdbs is that the signals at the destination chips are all going high at the same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described below. external feedback is the trait that allows for this compensation. since the pll on the zdb will cause the feedback signal to be in phase with the reference signal. when laying out the board, match the trace lengths between the output being used for feed back and the fbin input to the pll. if it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the fbin pin a little shorter or a little longer than the traces to the devices being clocked. inserting other devices in feedback path another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. this implem entation can be applied to any device (asic, multiple output clock buffer/driver, etc.) which is put into the feedback path. referring to figure 2 , if the traces between the asic/buffer and the destination of the clock signal(s) (a) are equal in length to the trace between the buffer and the fbin pin, the signals at the destination(s) device will be driven high at the same time the reference clock provided to the zdb goes high. synchronizing the other outputs of the zdb to the outputs form the asic/buffer is more complex however, as any propagation delay in the asic/buffer must be accounted for. 3 19 20 21 22 6 5 4 7 15 16 17 18 10 9 8 13 14 12 11 1 23 24 2 gnd gnd gnd gnd agnd fbin vdd q5 q6 q7 q8 q9 vdd avdd clk fbout oe vdd q4 q3 q2 q1 q0 vdd v dd vdd 0.1 f v dd v dd 10 f 3.3v 10 f fb fb cy2510 0.1 f 0.1 f 0.1 f 0.1 f figure 1. schematic reference signal feedback input asic/ buffer zero delay buffer a figure 2. six output buffers in the feedback path [+] feedback
cy2509/10 document #: 38-07230 rev. *c page 4 of 6 absolute maximum ratings [1] stresses greater than those listed in this table may cause permanent damage to the device. these represent a stress rating only. operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature und er bias ?55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : t a =0c to 70c, v dd = 3.3v 10% parameter description test condition min. typ. max. unit i dd supply current unloaded, 100 mhz ? ? 200 ma v il input low voltage ? ? 0.8 v v ih input high voltage 2.0 ? v dd +0.3 v v ol output low voltage i ol = 12 ma ? ? 0.8 v v oh output high voltage i oh = ?12 ma 2.1 ? ? v i il input low current v in = 0v ? ? 50 a i ih input high current v in = v dd ??50 a ac electrical characteristics: t a = 0c to +70c, v dd = 3.3v 10% parameter description test condition min. typ. max. unit f out output frequency 30-pf load [5] 40 ? 140 mhz t r output rise time 0.8v to 2.0v, 30-pf load ? ? 2.1 ns t f output fall time 2.0v to 0.8v, 30-pf load ? ? 2.5 ns t iclkr input clock rise time [2] ??4.5ns t iclkf input clock fall time [2] ??4.5ns t pej clk to fbin skew variation [3, 4] measured at v dd /2 ?350 0 350 ps t sk output to output skew all outputs loaded equally ?100 0 100 ps t d duty cycle 30-pf load 43 50 58 % t lock pll lock time power supply stable ? ? 1.0 ms t jc jitter, cycle-to-cycle ? 50 100 ps notes: 1. multiple supplies : the voltage on any input or i/o pin cann ot exceed the power pin during power-up. power supply sequencing is not required. 2. longer input rise and fall time will degrade skew and jitter performance. 3. skew is measured at v dd /2 on rising edges. 4. duty cycle is measured at v dd /2. 5. production tests are run at 133 mhz. [+] feedback
cy2509/10 document #: 38-07230 rev. *c page 5 of 6 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions spread aware is a trademark of cypress semiconductor corporat ion. all products and company names mentioned in this docu- ment may be the trademarks of their respective holders. ordering information ordering code package type temperature range cy2509zc-1 24-pin tssop commercial cy2509zc-1t 24-pin tssop - tape and reel commercial cy2510zc-1 24-pin tssop commercial CY2510ZC-1T 24-pin tssop - tape and reel commercial lead-free cy2509zxc-1 24-pin tssop commercial cy2509zxc-1t 24-pin tssop - tape and reel commercial cy2510zxc-1 24-pin tssop commercial cy2510zxc-1t 24-pin tssop - tape and reel commercial pin 1 id seating plane bsc. bsc 0-8 plane gauge 1 24 7.70[0.303] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 7.90[0.311] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] 24-lead thin shrunk small outline package (4.40-mm body) z24 51-85119-*a [+] feedback
cy2509/10 document #: 38-07230 rev. *c page 6 of 6 document history page document title: cy2509/10 spread aware? , ten/eleven output zero delay buffer document number: 38-07230 rev. ecn no. issue date orig. of change description of change ** 110495 01/07/02 szv change from spec number: 38-00914 to 38-07230 *a 122844 12/14/02 rbi power up requirements added to operating conditions information *b 352015 see ecn rgl added lead-free devices added typical jitter and max. v ih numbers *c 385383 see ecn rgl minor change: replaced the wrong package drawing [+] feedback
|
